/**************************************************
versys eda example--**** test.v ****---------------
---------------Test module of ram------------------
Copyright (c) 1996-2009, by all Contributions. 
All rights reserved.
***************************2009/06/22 lexim,inc.***/

`timescale	1ns/1ns

module test;

reg [7:0]	addr;
reg 		enable, readwr;
wire [15:0]	data;
reg [15:0]	data__in;
reg [7:0]	tmpad;
reg [15:0]	tmpwd;
integer		i;

assign	data = data__in;

ram	testram(addr, enable, readwr, data);

initial
begin
	$dumpfile("ram.vcd");
	$dumpvars(0,test);
		enable = 1;
		readwr = 0;
		tmpad  = 8'h08;
		tmpwd = 16'h000F;
		data__in = 16'hZZZZ;
	for(i=0; i<10; i=i+1) begin
			addr = tmpad;
		#20	readwr = 1; data__in = tmpwd;
		#20	readwr = 0;data__in = 16'hZZZZ;
		#20	tmpad  = tmpad + 1;
			tmpwd  = tmpwd - 1;
	end
		enable = 1;
		readwr = 0;
        	tmpad  = 8'h08;
        	tmpwd  = 16'h000F;
		data__in = 16'hZZZZ;

        for(i=0; i<10; i=i+1) begin
                	addr = tmpad;
                #60	tmpad  = tmpad + 1;
	end

	$finish;
end

endmodule