/**************************************************
versys eda example--**** test.v ****---------------
------------Test module of inverter-------------
Copyright (c) 1996-2007, by all Contributions. 
All rights reserved.
*******************2007/11/22 by ogu, lexim,inc.***/

`timescale	1ns/1ns

module test;

reg 	din;
wire	dout;

inverter	inva(din, dout);

integer	i;

initial
	begin
	$dumpfile("inverter.vcd");
	$dumpvars(0,test);
	$display("din | dout");
	$display("----------");
	for (i = 0; i <= 20; i = i + 1) begin
		if(i%2)
			din = 1;
		else
			din = 0;
		#50
		$display("%b | %b", din, dout);
	end
	$finish;
end

endmodule