/**************************************************
versys eda example--**** test.v ****---------------
----Test module of DFF with Synchronized reset-----
Copyright (c) 1996-2007, by all Contributions. 
All rights reserved.
*******************2007/11/22 by ogu, lexim,inc.***/

`timescale	1ns/1ns

module test;

reg 	clock, reset, din;
wire	dout;

dffr	dffr1(clock, reset, din, dout);

parameter	step = 16;
integer	i;

always	#(step/2)	clock = ~clock;

initial
	begin
	$dumpfile("dffr.vcd");
	$dumpvars(0,test);
			clock = 0;
			din = 0;
			reset = 0;
	#10		reset = 1;
	#30		reset = 0;
	for (i = 0; i <= 20; i = i + 1) begin
		#20		din = !din;
	end
	$finish;
end

endmodule