/**************************************************
versys eda example--**** dffr.v ****---------------
---Verilog module of DFF with Synchronized reset---
Copyright (c) 1996-2007, by all Contributions. 
All rights reserved.
*******************2007/11/22 by ogu, lexim,inc.***/

module	dffr(clock, reset, din, dout);
	input clock, reset, din;
	output dout;

	reg dout;

	always @(posedge clock)
	begin
		if (reset)
			dout <= 1'b0;
		else
			dout <= din;
	end
endmodule