/************************************************** versys eda example--**** test.v ****--------------- -------------Test module of counter---------------- Copyright (c) 1996-2007, by all Contributions. All rights reserved. *******************2007/11/22 by ogu, lexim,inc.***/ `timescale 1ns/1ns module test; reg clock, load, clear; reg [7:0] din; wire [7:0] dout; counter testcnt(clock, load, clear, din, dout); parameter step = 20; always #(step/2) clock = ~clock; initial begin $dumpfile("counter.vcd"); $dumpvars(0,test); clock = 0; load = 0; clear = 1; din = 8'h08; #60 clear = 0; #120 load = 1; #60 load = 0; #320 $finish; end endmodule