/************************************************** versys eda example--**** counter.v ****------------ ------------Verilog module of counter-------------- Copyright (c) 1996-2007, by all Contributions. All rights reserved. *******************2007/11/22 by ogu, lexim,inc.***/ module counter(clock, load, clear, din, dout); input clock, load, clear; input [7:0] din; output [7:0] dout; reg [7:0] countval; assign dout = countval; always @(posedge clock) begin if (clear) countval = 0; else if (load) countval = din; else countval = countval + 1; end endmodule