/**************************************************
versys eda example---**** test.cpp ****------------
-------------Test module of static ram-------------
Copyright (c) 1996-2009, by all Contributions. 
All rights reserved.
***************************************************
Verilator Version 3.710
inout data transrate to data and data__in

addr  --->|~~~~~~~|
enable--->|  ram  |<-->data
readwr--->|_______|
	 verilog module

	      || 
	      \/
addr  --->|~~~~~~~|-->data
enable--->|  ram  |
readwr--->|_______|<--data__in
	 systemc module

*************************2009/06/22 lexim,inc.*****/

#include <stdio.h>
#include <iostream>
#include "systemc.h"
#include "Vram.h"

int sc_main(int argc, char *argv[])
{
	int i;
	sc_signal<uint32_t > addr;
	sc_signal<bool> enable;
	sc_signal<bool> readwr;
	sc_signal<uint32_t > data;
	sc_signal<uint32_t > data__in;

	sc_int<8>  tmpad;
	sc_int<16> tmpwd;
	Vram *testram;
	testram = new Vram("testram");
	(*testram)(addr, enable, readwr, data, data__in);
	sc_trace_file *trace_f;
	trace_f = sc_create_vcd_trace_file("ram");
	((vcd_trace_file *)trace_f) -> sc_set_vcd_time_unit(-9);
	sc_trace(trace_f, addr, "addr");
	sc_trace(trace_f, enable, "enable");
	sc_trace(trace_f, readwr, "readwr");
	sc_trace(trace_f, data__in, "data__in");
	sc_trace(trace_f, data, "data");
	sc_initialize();
	enable = true;
	readwr = false;
	tmpad = 0x08;
	tmpwd = 0x0f;
	data__in =0x00;
	for(i=0; i<10; i++)
	{
		addr = tmpad;
		sc_start(20, SC_NS);
		readwr = true;
		data__in = tmpwd;
		sc_start(20, SC_NS);
		readwr = false;
		data__in =0x00;
		sc_start(20, SC_NS);
		tmpad += 1;
		tmpwd -= 1;
	}
	enable = true;
	readwr = false;
        tmpad = 0x08;
        tmpwd = 0x0f;
	data__in =0x00;
        for(i=0; i<10; i++)
        {
                addr = tmpad;
                sc_start(60, SC_NS);
                tmpad += 1;
        }
	sc_close_vcd_trace_file(trace_f);
	return 0;
}